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M61280M8-XXXFP
NTSC TV Signal Processor with MCU
REJ03F0053-0100Z Rev.1.0 Sep.23.2003
Features
* * * * * * * * * * * * 3 line composite video signal inputs and 1 line S video signal input are available Built-in 3 input audio switch with ATT output Correspond to digital OSD H output of emitter follower type (L at stopping, same as M61250BFP) Selectable of ACL/ABCL Built-in H OSC resonator Built-in vertical saw tooth generator Correspond to fsc clock output Built-in 5V & 8V regulator Built-in MCU reset circuit Built-in 8bit MCU ROM: 32kByte, RAM: 1152byte
Applications
* NTSC color television receivers
Pin Configuration
Package: 80P6U
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M61280M8-XXXFP
Block Diagram
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M61280M8-XXXFP
Absolute Maximum Ratings
Item Power supply voltage (ASIC) Power supply voltage (MCU) Input voltage (MCU: CNVSS) Input voltage (MCU: P00 to P07, P11 to P14, P20 to 27, P40 to P45, RESET, CVIN) Output voltage (MCU: P00 to P07, P11 to P14, P20 to 27, P40, P41) Circuit current (MCU: P11 to P14, P20 to P27, P40, P41) Circuit current (MCU: P00 to P07, P20 to P23, P40, P41) Circuit current (MCU: P11 to P14) Circuit current (MCU: P24 to P27) Power dissipation Thermal reduction Operating ambient temperature Storage temperature Symbol Vcc (ASIC) Vcc (MCU) VI (MCU) VI (MCU) Measured with reference to pin Vss. Output transistor in shut-off state. Condition Ratings 6.0, 10.0 -0.3 to 6 -0.3 to VCC+0.3 -0.3 to VCC+0.3 Unit V V V V
VO (MCU) IOH (MCU) IOL1 (MCU) IOL2 (MCU) IOL3 (MCU) Pd Kt Topr Tstg Ta = 25C
-0.3 to VCC+0.3 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 6 (Note 2) 0 to 10 (Note 2) 2000 20 -10 to 65 -40 to 125
V mA mA mA mA mW mW/C C C
Notes: 1. The sum of currents flowing from the IC should not exceed 20 mA. 2. The sum of currents flowing into the IC (IOL1+IOL2) should not exceed 30 mA. 3. Pin names for the different quantities are given as follows. (1) Dedicated pins: Dedicated pin name (2) Double/triple-function ports *When standards are the same: I/O port name *When standard of functions other than the I/O port are different: function pin name
Recommended Operating Conditions
Item Power supply voltage (MCU) (Note 1) Power supply voltage1 (ASIC: Pin22) Power supply voltage2 (ASIC: Pin47) Power supply voltage3 (ASIC: Pin49) Power supply voltage4 (ASIC: Pin31) Power supply voltage (MCU) ""H" input voltage (MCU: P00 to P07, P11 to P14, P20 to P27, P40 to P45, RESET) "H" input voltage (MCU: SCL1, SCL2, 2 SDA1, SDA2)(using I C-BUS) "L" input voltage (MCU: P00 to P07, P11 to P14, P20 to P27, P40 to P45) "L" input voltage (MCU: SCL1, SCL2, 2 SDA1, SDA2)(using I C-BUS) "L" input voltage (Note 2) (MCU: RESET, TIM3, INT1, INT2, INT3, SIN, SCLK) "H" output average current (Note 3) (MCU:P10 to P16, P20 to 27) Symbol VDD(MCU) Vcc1(ASIC) Vcc2(ASIC) Vcc3(ASIC) Vcc4(ASIC) VSS VIH1 Min. 4.75 4.75 7.6 7.6 8.3 0 0.8VDD Typ. 5.0 5.0 8.0 8.0 8.7 0 -- Max. 5.25 5.25 8.4 8.4 9.1 0 VDD Unit V V V V V V V
VIH2 VIL1 VIL2 VIL3
0.7VDD 0 0 0
-- -- -- --
VDD 0.4VDD 0.3VDD 0.2VDD
V
V V
IOH
--
--
1
mA
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M61280M8-XXXFP
Recommended Operating Conditions (cont.)
Item "L" output average current (Note 4) (MCU:P00 to P14, P20 to P23) "L" output average current (Note 4) (MCU:P11 to P14) "L" output average current (Note 5) (MCU:P24 to P27) Oscillation frequency (CPU operation) (Note 6) (MCU: XIN) Oscillation frequency (subclock operation) (MCU: XCIN) Input frequency (MCU:TIM3, INT1, INT2,.INT3 ) Input frequency (MCU: SCLK) Input frequency (MCU: SCL1,SCL2) Input amplitude (MCU: TV video signal CVIN) Symbol IOL1 IOL2 IOL3 f(XIN) f(XCIN) fhs 1 fhs 2 hs 3 VI Min. -- -- -- 7.9 29 -- -- -- 1.5 Typ. -- -- -- 8.0 32 -- -- -- 2.0 Max. 2 6 10 8.1 35 100 1 400 2.5 Unit mA mA mA MHz kHz kHz MHz kHz V
Notes: 1. In order to eliminate power supply noise, a 0.1 F or greater capacitor should be connected externally across power supply pins VDD and VSS. In addition, a 0.1 F or greater capacitor should also be connected across VDD and CNVSS. (The recommended crystal oscillator is Murata model no. CSA8.00MTZ (8.00 MHz), shown in the measurement circuit diagram.) 2. Pin names for the different quantities are given as follows. (1) Dedicated pins: Dedicated pin name (2) Double/triple-function ports *When standards are the same: I/O port name *When standard of functions other than the I/O port are different: function pin name 3. The sum of currents flowing from the IC should not exceed 20 mA. 4. The sum of currents flowing into the IC (IOL1+IOL2) should not exceed 30 mA. 5. The sum of the average currents of ports P24 to P27 flowing into the IC should not exceed 20 mA. 6. When using a CPU oscillation circuit (XIN, XOUT), a crystal oscillator or a ceramic resonator should be used.
Thermal Derating (Maximum Rating)
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M61280M8-XXXFP
I2C Bus Table
1. Slave Address = BAH (WRITE), BBH (READ)
A6 1 A5 0 A4 1 A3 1 A2 1 A1 0 A0 1 R/W 1/0
2. Write Table (input bytes)
3. Read Table (output byts)
D7 KILLERB D6 2WIN WIDEB D5 VFREEB D4 VCONIB D3 0 D2 0 D1 HCOINB D0 1
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M61280M8-XXXFP 4. Bus Functions * Write
Function Audio Audio ATT Audio SW Audio Mute Video Video Tone Contrast Control OSD Contras Clip Y DL Time Adj Y DL Fine Adj Vidio SW Y SW LPF Vidio Mute TRAP Off C-TRAP Adj Black Stretch Off Black Stretch Cont Bit 7 2 1 6 7 1 2 1 3 1 1 1 2 1 3 Sub Add DATA 10H 11H 10H 0AH 00H 00H 0CH 0CH 0BH 0CH 0AH 07H 1DH 0BH 0BH D0-D6 D0-D1 D7 D0-D5 D0-D6 D7 D0-D1 D2 D3 D3 D7 D3 D0-D1 D7 D4-D6 Discription Pin 34 audio output level adjustment Audio input switching; 0: Audio 1, 1: Audio 2, 2: Audio 3 Pin 34 audio output on/off (mute) switching; 0: audio on (non-muted), 1: mute Sharpness level control Contrast level control OSD (EXT RGB) contrast lower-limit clipping on/off; 0: clipping on, 1: clipping off Y signal delay adjustment Y signal delay fine adjustment Video input pins 26/24/20/30 switching; 0: pin 26, 1: pin 24, 2: pin 20, 3: pin 30 Pin 14 (Y SW OUT) output f-characteristic switching; 0: flat, 1: LPF (fc = 700 kHz) Y signal chroma trap on/off switching; 0: trap on, 1: trap off Chroma trap frequency fine adjust Black stretch circuit on/off switching; 0: black stretch on, 1: black stretch off Black stretch charge, discharge time constant adjustment; D4, D5: charge time constant adjustment; D6: discharge time constant adjustment Black stretch discharge time constant adjustment; discharge time constant adjustment Hue control Color level control Chroma BPF take-off function on/off switching; 0: BPF; 1: take off Color demodulation angle switching; 0: 103 deg, 1: 95 deg Colorkiller sensitivity switching (active shallow direction); 0: 40 dB, 1: 35 dB Forced b/w mode; 0: normal; 1: b/w Forced color mode; 0: normal; 1: color X'tal oscillation circuit forced free-running mode; 0: off, 1: free-running Bright level control R output level control B output level control R output DC level control G output DC level control B output DC level control Blue back screen on/off switching; 0: off, 1: blue back White raster on/off switching; 0: off, 1: white back ABCL on/off switching; 0: off, 1: ABCL on ABCL sensitivity low/high switching; 0: low, 1: hi OSD level switching; 0: normal, 1: -8% ACL on/off switching; 0: normal, 1: ACL max Halftone on/off switching; 0: normal, 1: halftone FASTBLK switching; 0: normal, 1: hi (full-screen OSD mode) Initial Note 00H X0H 0 20H 40H 0 X0H 0 X0H 0 V Latch V Latch V Latch V Latch
Y signal output on/off (mute) switching; 0: mute off, 1: mute 0 0 X0H 0 0XH
Black Dicharge2 CHROMA Tint Control Color Control Take Off C Angle95 Killer Level Force Mono Force Color Fsc Free RGB Brightness Control Drive (R) Drive (B) Cut Off (R) Cut Off (G) Cut Off (B) Blue Back WhiteBack ABCL ABCL Gain OSD Bright ACL OFF HTONE FASTBLK Hi
1 7 7 1 1 1 1 1 1 8 7 7 8 8 8 1 1 1 1 1 1 1 1
1DH 08H 09H 07H 0CH 07H 02H 1DH 07H 01H 02H 03H 04H 05H 06H 09H 03H 07H 07H 1FH 07H 07H 0BH
D3 D0-D6 D0-D6 D0 D4 D1 D7 D2 D6 D0-D7 D0-D6 D0-D6 D0-D7 D0-D7 D0-D7 D7 D7 D5 D4 D3 D7 D2 D3
0XH 40H 40H 0 0 0 0 0 0 80H 40H 40H 80H 80H 80H 0 0 0 0 0 0 0 0 V Latch V Latch V Latch
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M61280M8-XXXFP * Write (cont.)
Function DEF AFC2 H Phase V Out Stop Service SW H Start AFC1 Gain AFC2 Gain Down H VCO Adj V Shift V-Size H-free V-free S Slice Down Slice Det Down HV BLK OFF Bit 4 1 1 1 3 1 3 3 6 1 1 2 1 1 Sub Add DATA 0FH 0EH 0DH 0FH 12H 0FH 1CH 0DH 0EH 0FH 0EH 0DH 0DH 0AH 12H 0CH 08H 1EH 11H D0-D3 D7 D7 D7 D0-D2 D4 D0-D2 D0-D2 D0-D5 D6 D6 D4-D5 D6 D6 D3 D7 D7 D0-D2 D4-D7 Discription Screen horizontal position adjustment Pin 38 VOUT (ramp) forced stop mode (when stopped, pin 38 at DC GND level); 0: VOUT, 1: STOP Vertical output on/off switching; 0: vertical output on, 1: vertical output off Horizontal output out/stop switching; 0: stop, 1: H out Horizontal AFC gain adjustment; 000: low to 111: hi Horizontal AFC2 gain high/low switching; 0: high, 1: low H VCO free-running frequency adjustment Vertical ramp start timing adjustment Vertical ramp amplitude adjustment Horizontal output forced free-running mode on/off switching; 0: off, 1: horizontal free-running Vertical output forced free-running mode on/off switching; 0: off, 1: vertical free-running Sync detection slice level switching (0: 50%, 1: 30%, 2: 40%, 3: 25%) 0: normal, 1: lower sync detection sensitivity (end of video signal only) Horizontal/vertical blanking on/off switching; 0: blanking on, 1: blanking off Vertical minimum sync detection width switching; 0: sync detect width =18 s, 1: sync detect width =14 s Vertical sync detection switching (1 window/2 windows); 0: 2 windows, 1: 1 window Internal BGP on/off switching when no FBP input; 0: BGP on, 1: BGP off C-sync output LPF cutoff frequency adjustment Pin 18 intelligent monitor mode switching Initial Note X8H 0 0 0 X4H 0 X4H X0H 20H 0 0 0XH 0 0 0 0 0 X0H 0XH
V SYNC DET TIME 1 V1 Window BGPFBP OFF C-SYNC Adj Monitoring 1 1 3 4
* Read
HCONB -- -- VCOINB VFREEB 2WIN WIDEB KILLERB 1 1 1 1 1 1 1 00H 00H 00H 00H 00H 00H 00H D1 D2 D3 D4 D5 D6 D7 Horizontal sync detection; "1" when asynchronous 0 0 Vertical sync detection; "1" when asynchronous V free-running mode; 0: V free-running, 1: V lock Vertical 2-window detection; 0: wide window, 1: narrow window Colorkiller information output; "1" when killer off
Note: Functions not listed in this bus function table are used only in testing, and operation is not guaranteed.
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M61280M8-XXXFP
Test Circuit
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M61280M8-XXXFP
Input Signals
1. Video/Chroma/RGB/DEF Block
SG No. SG. A Signal Description (75 termination) NTSC format APL 100% standard video signal. Vertical signal is interlaced at 60 Hz.
SG. B
In the SG.A signal, the Lumi. signal frequency and amplitude can be changed. However, standard amplitude is 0.714 Vp-p. In the figure on the right, the Lumi. signal is represented by f.
SG. C
NTSC standard monochrome video signal. Vertical signal is interlaced at 60 Hz.
SG. D
NTSC format video signal; APL variable. Vertical signal is interlaced at 60 Hz.
SG. E
NTSC format monochrome video signal. In the SG.C signal, the burst and chroma part frequency and amplitude can be changed. Vertical signal is interlaced at 60 Hz. (Standard state: Veb = 0.286 V, Vec = 0.572 V, feb = fec = 3.579545 MHz)
SG. F
Fast blanking signal; synchronized with video input signal.
External RGB (OSD) signal; synchronized with video input signal and blanking signal.
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M61280M8-XXXFP 1. Video/Chroma/RGB/DEF Block (cont.)
SG No. SG.G SG. H Signal Description (75 termination) NTSC format rainbow color bar video signal. Vertical signal is interlaced at 60 Hz. Duty 90%, variable frequency, variable level. (Standard horizontal frequency = 15.734 kHz, vertical frequency = 60 Hz, 1 Vp-p)
SG. I
Duty variable (standard 95%), frequency variable, level variable (Standard: horizontal frequency = 15.734 kHz, vertical frequency = 60 Hz, 1 Vp-p)
SG. J
NTSC format standard color bar video signal; vertical signal is interlaced at 60 Hz.
SG. K SG. L
NTSC format, standard 8-step wave signal; vertical signal is interlaced at 60 Hz. NTSC format red raster signal; vertical signal is interlaced at 60 Hz.
2. Audio Block
SG No. SG.AU Signal Description (50 termination) fo = 400 Hz, 500 mVrms, CW
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M61280M8-XXXFP
Setup Instructions for Evaluation PCB
1. Horizontal Blanking Pulse Adjustment The horizontal blanking pulse timing and pulse width are adjusted using the variable resistances of a one-shot multivibrator, as shown below.
The timing is adjusted to 8 s using the pin 15 variable resistance of the M74LS221P TTL IC. Also, the pulse width is adjusted to 12 s using the pin 7 variable resistance.
2. H VCO Adjustment Prior to measurement of the M61280Mx-xxxFP, the following method is used for H VCO adjustment. 1. The H VCO control I C bus data (1 CH D0-D2) is adjusted, and the pin 46 (H OUT) frequency is set to approx. 15.734 kHz.
2
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M61280M8-XXXFP
Electrical Characteristics, ASIC
(Ta = 25C)
Imput signal Symbol ICC ICC5V ICC8V ICC12 ICC49 ICC31 Power Vth9 V40H V40L V28 V18H1 V18H2 Reset V13H V13L TH9 Item Standard conditions 5 V circuit current (pin 22) 8 V circuit current Pin 47 circuit current Pin 49 circuit current Pin 31 circuit current Power supply circuit standard conditions Power on control threshold voltage 8.7 VREG output voltage 1 8.7 VREG output voltage 2 5.7 VREG output voltage 1 MCU 5.7 VREG output voltage 1 MCU 5.7 VREG output voltage 2 Reset standard conditions Maximum reset output voltage Minimum reset output voltage Reset threshold voltage I2C standard conditions ACK current SCL/SDA VTH (L) SCL/SDA VTH (H) Clock frequency -- -- -- -- -- -- 13 13 9 4.5 -- 4 5 0 4.2 5.5 0.5 4.4 V V V -- -- -- -- -- -- -- -- -- -- -- -- 9 40 40 28 18 18 2.6 8.3 -- 5.55 5.45 5.45 3 8.7 0 5.8 5.7. 5.7 3.4 9.1 0.3 6.05 5.95 5.95 V V V V V V Pin 9 = 5 V Pin 9 = 0 V Pin 9 = 5 V Pin 9 = 5 V Pin 9 = 0 V Pins 4, 7 = 5 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V -- -- -- -- -- -- -- -- -- -- 22 47,48, 49 47 49 31 40 27 -- -- 3 55 42 23 19 6 70 57 -- -- 9 mA mA mA mA mA Pin SG Test point Limits Min Typ Max Unit Notes Pins 4, 7=0 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V MCU/VIDEO/Chroma Vcc Deflection/RGB Drive 8 V Vcc Reference data; Deflection/Vcc Reference data; RGB Drive/AUDIO 8 V Vcc 8.7 VREG Vcc Pins 4, 7 = 5 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V
I2C IACK VIL VIH FSCL
-- -- -- -- --
-- -- -- -- --
--
-- --
-- 1 0.75 4.25 --
-- -- 1.5 5.0 100
-- mA V V kHz Reference data
56,58 56,58 56
0.0 3.5 --
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M61280M8-XXXFP
Imput signal Symbol AUDIO GEAu1 GEAu2 GEAu3 VOL-max VOL-min Item AUDIO standard conditions Audio gain1 Audio gain2 Audio gain3 Maximum audio output amplitude Maximum audio output attenuation 27 25 21 27 27 SG.AU SG.AU SG.AU SG.AU SG.AU Pin SG
Test point
Limits Min Typ Max Unit Notes Pins 4, 7 = 5 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V
34 34 34 34 34
-3 -3 -3 350 --
0 0 0 500 -65
3 3 3 720 -60
dB dB dB mVms dB
Expressed as 20 log (measured value/input amplitude) Expressed as 20 log (measured value/input amplitude) Expressed as 20 log (measured value/input amplitude)
Expressed as 20 log (measured value / input amplitude)
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M61280M8-XXXFP
Imput signal Symbol VIDEO 2AGV1 2AGV2 2AGV3 2AGVY Ymax GY FBY CRF1 CRF2 YDL1 YDL2 YDL3 YDL4 Gtnor GTmax GTmin GT2M GT5M BLS VMF Item Video standard conditions Video SW1 output level (CVBS1 input) Video SW2 output level (CVBS2 input) Video SW3 output level (CVBS3 input) Video SWY output level (Y/C input) Maximum video output Video gain Video frequency characteristic Chroma trap attenuation 1 Chroma trap attenuation 2 YDL time 1 YDL time 2 YDL time 3 YDL time 4 Video tone control characteristic 1 Video tone control characteristic 2 Video tone control characteristic 3 Video tone control characteristic 4 Video tone control characteristic 5 Black stretch characteristic Video mute function Pin -- 26 24 20 30 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 SG -- SG.A SG.A SG.A SG.A SG.A SG.A SG.B SG.C SG.L SG.A SG.A SG.A SG.A SG.B SG.B SG.B SG.B SG.B SG.K SG.A
Test point -- 14 14 14 14 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52
Limits Min -- 1.6 1.6 1.6 1.6 2.9 12 -4 -- -- 190 100 100 100 1.0 7 -6 -1 -9 0.01 -- Typ -- 2.0 2.0 2.0 2.0 4.2 15 -1 -- -- 260 150 150 150 1.4 10 -2 2 -5 0.03 -45 Max -- 2.6 2.6 2.6 2.6 5.6 18 -- -18 -6.5 330 250 250 250 1.8 14 2 5 -1 0.05 -35 Unit -- Vpp Vpp Vpp Vpp V dB dB dB dB ns Ns ns ns V dB dB DB dB V dB YDL2 = measured value - YDL1 measured value YDL3 = measured value - YDL2 measured value YDL4 = measured value - YDL3 measured value f = 2.5 MHz f = 2.5 MHz f = 2.5 MHz f = 2 MHz f = 5 MHz f = 5 MHz, C-trap: OFF Notes Pins 4, 7 = 5 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V
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M61280M8-XXXFP
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M61280M8-XXXFP
Imput signal Symbol CHROMA CnorR CnorB ACC1 ACC2 OV VikN KillP APCU APCL R/BN R-YN1 R-YN2 TC1 TC2 Ffsc Vfsc Ffscfree Vfscfree Item Chroma standard conditions Chroma standard output (R-Y) Chroma standard output (B-Y) ACC characteristic 1 ACC characteristic 2 Chroma overload characteristic Killer operation input level Color remaining on colorkilling APC pull-in range (upper) APC pull-in range (lower) Demodulation ratio Demodulation angle 1 Demodulation angle 2 TINT control characteristic 1 TINT control characteristic 2 fsc output frequency fsc output amplitude fsc output frequency in fsc free mode fsc output amplitude in fsc free mode Pin -- 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 SG -- SG.C SG.C SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.C SG.C SG.C SG.C
Test point -- 33 33 33 33 33 33 33 33 33 33 33 33 33 33 32 32 32 32
Limits Min -- 390 640 -3 -6.5 -3 -- -- 300 -- 0.40 86 78 30 30
3.5793
Typ -- 560 920 0 0 2 -40 -45 600 -600 0.57 103 95 45 45
3.5796
Max -- 790 1290 3 1.5 5 -35 -30 -- -300 0.80 120 112 60 60
3.5799
Unit -- mVpp mVpp dB dB dB dB dB Hz Hz -- deg deg deg deg MHz mVpp MHz mVpp
Notes Pins 4, 7 = 5 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V
Veb, Vec: standard input level +6 dB Veb, Vec: standard input level -18 dB Vec = 800 mV Veb, Vec: variable Veb = 0 mV feb = fec: variable feb = fec: variable feb = feb + 50 kHz feb = feb + 50 kHz feb = feb + 50 kHz feb = feb + 50 kHz feb = feb + 50 kHz
250
3.5790
500
3.5795
800
3.5810
250
500
800
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M61280M8-XXXFP
Symbol RGB VBLK Gytyp GYmin GYEnor GYEmin GYEclip Lum nor Lum max Lum min D(R)1 D(B)1 D(R)2 D(B)2 EXD1(R) EXD1(G) EXD1(B) EXD1(R-G) EXD1(G-B) EXD1(B-R) EXD2(R-G)
EXD2(G-B)
OFRG OFBG C(R)1 C(G)1 C(B)1 C(R)2 C(G)2
Item RGB standard conditions Output blanking voltage Contrast control characteristic 1 Contrast control characteristic 2 Contrast control characteristic 3 Contrast control characteristic 4 Contrast control characteristic 5 Brightness control characteristic 1 Brightness control characteristic 2 Brightness control characteristic 3 R driving control characteristic 1 B driving control characteristic 1 R driving control characteristic 2 B driving control characteristic 2 Digital OSD (R) I/O characteristic 1 Digital OSD (G) I/O characteristic 1 Digital OSD (B) I/O characteristic 1 Digital OSD (R-G) amplitude difference Digital OSD (G-B) amplitude difference Digital OSD (B-R) amplitude difference Digital OSD black level DC voltage difference (R-G) Digital OSD black level DC voltage difference (G-B) Offset voltage (R-G) Offset voltage (B-G) R cutoff control characteristic 1 G cutoff control characteristic 1 B cutoff control characteristic 1 R cutoff control characteristic 2 G cutoff control characteristic 2
Imput signal Pin SG -- -- 26 26 26 26 26 59,60, 61 26 26 26 26 26 26 26 61,65, 26 61,65, 26 61,65, 26 -- -- -- -- SG.A SG.B SG.B SG.A SG.A SG.F SG.D SG.D SG.D SG.A SG.A SG.A SG.A SG.F, SG.A SG.F, SG.A SG.F, SG.A -- -- -- SG.F
Test point -- 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50,51, 52 50 52 50 52 50 51 52 -- -- -- 50,51
Limits Min Typ -- -- 0 2.2 -- 2.2 -- 0.50 1.7 2.3 -- 2.0 2.0 -5.0 -5.0 1.0 1.0 1.0 -350 -350 -350 -250 0.1 2.8 200 2.8 100 0.65 2.1 3 1.3 4.0 4.0 -3.0 -3.0 1.5 1.5 1.5 0 0 0 0
Max -- 0.3 3.3 300 3.3 200 0.80 2.5 -- 2 6.0 6.0 -1.0 -1.0 2.0 2.0 2.0 350 350 350 250
Unit -- V Vpp mVpp Vpp mVpp Vpp V V V dB dB dB dB Vpp Vpp Vpp mV mV mV mV
Notes Pins 4, 7 = 5 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V
f = 100 kHz f = 100 kHz Pin 53 = 2.9 V Pin 53 = 0.0 V Pin 65 = 2.0 V Vy = 0.0 V Vy = 0.0 V Vy = 0.0 V
Vosd = 1.0 V, SW61 = ON Vosd = 1.0 V, SW60 = ON Vosd = 1.0 V, SW59 = ON
--
SG.F
51,52
-250
0
250
mV
26 26 26 26 26 26 26
SG.D SG.D SG.D SG.D SG.D SG.D SG.D
50,51 51,52 50 51 52 50 51
-100 -100 2.6 2.6 2.6 1.1 1.1
0 0 2.9 2.9 2.9 1.4 1.4
100 100 3.2 3.2 3.2 1.7 1.7
mV mV V V V V V
Vy = 0.0 V Vy = 0.0 V Vy = 0.0 V Vy = 0.0 V Vy = 0.0 V Vy = 0.0 V Vy = 0.0 V
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M61280M8-XXXFP
Imput signal Symbol C(B)2 Ccon1 Ccon2 Ccon3 MTXRB MTXGB DOSD1 DOSD2 BB(R) BB(G) BB(B) WB WBL-RB WBL-GB Item Pin 26 26 26 26 26 26 61,65, 26 61,65, 26 26 26 26 26 26 26 SG SG.D SG.C SG.C SG.C SG.G SG.G SG.F, SG.A SG.F, SG.A SG.A SG.A SG.A SG.A SG.A Y=30% SG.A Y=30%
Test point 52 51 51 51 50,52 51,52 50 50 50 51 52 50,51, 52 50,52 51,52
Limits Min 1.1 2 -- -- 0.81 0.29 -- -- 1.7 1.7 2.7 2.7 -80.0 - Typ 1.4 5 -15 -40 0.98 0.37 0.05 0.05 2.1 2.1 3.7 3.7 -20.0 10.0 Max 1.7 8 -10 -35 1.08 0.45 0.13 0.13 2.5 2.5 4.7 4.7 10.0 80.0 Unit V dB dB dB -- --
s s
Notes Vy = 0.0 V
Vosd = 1.0 V, SW59 = ON Vosd = 1.0 V, SW59 = ON
V V V V mV mV White level difference with, without burst, with reference to pin 52 (Bout) White level difference with, without burst, with reference to pin 52 (Bout)
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M61280M8-XXXFP
Imput signal Symbol DEF fH1 fH2 fH3 Hfree Item Deflection system standard conditions Horizontal freerunning frequency 1 Horizontal freerunning frequency 2 Horizontal freerunning frequency 3 Forced horizontal free-running operation Horizontal pull-in range (upper) Horizontal pull-in range (lower) Horizontal pulse timing 1 Horizontal pulse timing 2 Horizontal pulse width Horizontal pulse amplitude Horizontal pulse stop operation AFC gain operation Vertical free-running frequency Forced vertical freerunning operation Service mode operation Vertical pull-in frequency (upper) Vertical pull-in frequency (lower) Vertical ramp size Vertical ramp size control range 1 Vertical ramp size control range 2 Vertical ramp position control range 1 Vertical ramp position control range 2 Vertical blanking width Minimum width in minimum sync operation Pin -- -- -- -- 26 SG -- -- -- -- SG.A
Test point -- 46 46 46 46
Limits Min -- 15.3 14.7 15.8 15.3 Typ -- 15.7 15.1 16.2 15.7 Max -- 16.1 15.5 16.6 16.1 Unit -- kHz kHz kHz kHz In Hfree operation (0FH: D6 = 1) Notes Pins 4, 7 = 5 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V
FPHU FPHL HPT1 HPT2 HPTW VH HSTOP AFCG fV Vfree SVC FPVU FPVL VRsi1 VRsc1 VRsc2 VRpo1 VRpo2 VBLKW WVSS
26 26 26 26 -- -- -- 26 -- 26 -- 26 26 26 26 26 26 26 26 26
SG.H SG.H SG.A SG.A -- -- -- SG.A -- SG.A -- SG.H SG.H SG.A SG.A SG.A SG.A SG.A SG.A SG.I
46 46 46 46 46 46 46 43 38 38 38 38 38 38 38 38 38 38 50,51, 52 38
250 -- 4.5 3.5 21 4.7 -- 2.0 55 55 1.0 63 -- 1.6 2.0 0.8 18 805 1.32 14
500 -500 6.0 5.0 25 5.4 0.0 3.0 60 60 1.5 67 55 2.0 2.4 1.2 38 825 1.47 --
-- -250 7.5 6.5 29 -- 0.5 10.0 65 65 2 -- 57 2.4 2.8 1.6 58 845 1.62 --
Hz Hz
s s s
Variable input frequency Variable input frequency
V V dB Hz Hz V Hz Hz Vpp Vpp Vpp
s s
When OFH: D7 = 0, confirm that horizontal pulse is stopped When 12H is 03, 07, measure and compute amplitude
In Vfree operation (0EH: D6 = 1)
Variable input frequency Variable input frequency
Measured value - VRpo 1
ms
s
Variable input signal duty
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M61280M8-XXXFP
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M61280M8-XXXFP
Imput signal Symbol Monitoring Item Intelligent monitor system standard conditions Intelligent monitor 1 (composite sync) Intelligent monitor 6 (video SW output) Intelligent monitor 7 (G out) Intelligent monitor 8 (R out) Intelligent monitor 9 (B out) Intelligent monitor 10 (ACL) Intelligent monitor 11 (V sync) Intelligent monitor 12 (H out) Intelligent monitor 14 (DEF Vcc) Intelligent monitor 15 (video/chroma Vcc) Intelligent monitor 16 (Hi Vcc) Pin -- SG --
Test point --
Limits Min -- Typ -- Max -- Unit -- Notes Pins 4, 7 = 5 V; pins 9, 10 = 5 V; pins 23, 65 = 0 V; pins 47, 49 = 8 V Reference data Reference data Reference data. Amplitude measured from blanking level Reference data. Amplitude measured from blanking level Reference data. Amplitude measured from blanking level Reference data Reference data Reference data Reference data Reference data Reference data
MONI1 MONI6 MONI7 MONI8 MONI9 MONI10 MONI11 MONI12 MONI14 MONI15 MONI16
26 26 26 26 26 -- 26 26 -- -- --
SG.A SG.A SG.A SG.A SG.A -- SG.A SG.A -- -- --
33 33 33 33 33 33 33 33 33 33 33
-- -- -- -- -- -- -- -- -- -- --
4.9 0.95 2.0 2.0 2.0 4.3 4.0 3.0 2.90 2.70 2.90
-- -- -- -- -- -- -- -- -- -- --
V Vpp Vpp Vpp Vpp V Vpp Vpp V V V
* Intelligent Monitor Map 1. Sub Address: 11HD4 - D7 2. Output Pin: Pin33 3. Specification
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 11H HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F 11H D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Signal Composite Sync -- -- -- -- Y SW OUT G OUT R OUT B OUT ACL/ABCL V SYNC H OUT DEF VCC DEF VCC V/C VCC HI VCC
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M61280M8-XXXFP
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M61280M8-XXXFP
Method of Measurement of Electrical Characteristics
Video Clock 2AGTV1-3 video SW output level (CVBS1-3 input) 2AGEVY video SW output level (Y input) 1. Input SG.A to pin 26 (CVBS1), or pin 24 (CVBS2), or pin 20 (CVBS3), or pin 30 (Yin). 2. The amplitude (p-p) at pin 14 is measured. * In order to select TV or external input, use the subaddress 0BH. Y max maximum video output 1. Input SG.A to pin 26. 2. Measure the amplitude (p-p) other than the blanking part of the output of pins 50, 51, 52.
FBY video frequency characteristic 1. Input SG.B (5 MHz, 0.4 Vp-p) to pin 26. 2. Measure the amplitude (p-p) other than the blanking part of the output of pins 50, 51, 52, take the result to be YB. 3. FYB is defined as follows.
CRF1 chroma trap attenuation 1 (normal R/G/B output) TRF maximum chroma trap attenuation 1. Input SG.C to pin 26, measure the 3.58 MHz frequency level with TRAP ON/OFF (07H D3) DATA 1, take his to be N0. 2. Also measure the level with TRAP ON/OFF (07H D3) DATA 0. 3. CRF1 is defined as follows.
4. Take the minimum value of CRF1 when the I C BUS data of the TRAP fine ADJ (12H D0 / D1) is adjusted to be TRF. CRF2 chroma trap attenuation 2 (normal R / G / B output) 1. Input SG.L to pin 26. The input 3.58 MHz frequency level is N1. 2. Measure the 3.58 MHz frequency level when TRAP ON/OFF (07H D3) DATA 0. 3. CRF2 is defined as follows.
2
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M61280M8-XXXFP YDL1: YDL time 1 1. Input SG.A to pin 26. 2. Measure the delay time relative to the input signal of pins 50, 51, 52.
The delay time at 50% rise level is measured.
YDL2, 3, 4: YDL time 2, 3, 4 1. Input SG.A to pin 26. 2. Measure the delay time of the input signal and the pin 50, 51, 52 output signals. 3. YDL2, YDL3, YDL4 are defined as follows.
YDL2 = measured value (ns) - YDL1 (measured value) YDL3 = measured value (ns) - YDL2 (measured value) YDL4 = measured value (ns) - YDL3 (measured value)
GTmax video tone control characteristic 2 1. 2. 3. 4. Input SG.B (f = 2.5 MHz) to pin 26. The output amplitude of pins 50, 51, 52 when the video tone data is at the center (20 H) is taken to be GTnor. The output amplitude of pins 50, 51, 52 when the video tone data is maximum is measured. GTmax is defined as follows.
GTmin video tone control characteristic 3 1. 2. 3. 4. Input SG.B (f = 2.5 MHz) to pin 26. The output amplitude of pins 50, 51, 52 when the video tone data is at the center (20 H) is taken to be GTnor. The output amplitude of pins 50, 51, 52 when the video tone data is minimum is measured. GTmin is defined as follows.
GT2M video tone control characteristic 4 1. 2. 3. 4. Take pin 50, 51, 52 output amplitude when input signal frequency is 2.5 MHz to be GTnor. Input SG.B (f = 2 MHz) to pin 26. Measure pin 50, 51, 52 output amplitude. GT2M is defined as follows
Rev.1.0, Sep.23.2003, page 27 of 53
M61280M8-XXXFP GT5M video tone control characteristic 5 1. 2. 3. 4. Take pin 50, 51, 52 output amplitude when input signal frequency is 2.5 MHz to be GTnor. Input SG.B (f = 2 MHz) to pin 26. Measure pin 50, 51, 52 output amplitude. GT5M is defined as follows.
BLS black stretch characteristic 1. Input SG.K to pin 26. 2. With black stretch off (0BH D7 = 1), adjust the contrast (00H) and brightness (01H), and set the pin 50, 51, 52 output level of the first stage (lowest stage) to 2.0 V, and the output level of the eighth stage (highest stage) to 4.6 V. 3. Change black stretch to on (0BH D7 = 0), and measure the pin 50, 51, 52 first stage output level. 4. BLS is defined as follows.
VMF video mute function 1. Input SG.A to pin 26. 2. With the mute switch (0AH D7) on "VMFon", off "VMFoff", measure the output amplitude. 3. VMF is defined as follows.
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M61280M8-XXXFP Chroma Block CnorR chroma standard output (R-Y) CnorB Chroma standard output (B-Y) 1. Input SG.C to pin 26. 2 2. When "test mode" I C data is 1FH D2=1, 1DH D5=1, take the pin 33 output amplitude when 1DH D6 = 1, D7 = 1 and D6=0, D7=1 to be the chroma standard output (R-Y) and chroma standard output (B - Y), respectively. ACC1 ACC characteristic 1 1. Input SG.E (eb = 570 mV: level + 6 dB) to pin 26. 2. Measure the pin 33 output amplitude. 3. ACC1 is defined as follows.
ACC2 ACC characteristic 2 1. Input SG.E (input level: -18 dB) to pin 26. 2. Measure the pin 33 output amplitude. 3. ACC2 is defined as follows.
OV chroma overload characteristic 1. Input SG.E (eb = 800 mVp-p: chroma + 3 dB) to pin 26. 2. Measure the pin 33 output amplitude. 3. OV is defined as follows.
VikN killer operation input level 1. Input SG.E (variable level) at input level 0 dB to pin 26. 2. While monitoring the pin 33 output amplitude, lower the input level, and measure the input level when the output amplitude vanishes.
Rev.1.0, Sep.23.2003, page 29 of 53
M61280M8-XXXFP KillP hue remaining with killer 1. Input SG.E (level: -40 dB) to pin 26. 2. Measure the pin 33 output amplitude. APCU APC pull-in range (upper) APCL APC pull-in range (lower) 1. Input SG.E (feb-fec-3.579545 MHz) to pin 26. 2. After raising the frequency until the output from pin 33 vanishes, lower the frequency, and take the point at which an output appears to be fu. 3. After lowering the frequency until the output from pin 33 vanishes, raise the frequency, and take the point at which an output appears to be fl. 4. APCU and APCL are defined as follows.
APCU = fu - 3579545 Hz APCL = fl - 3579545 Hz
R/BN demodulation ratio R-Y/B-Y 1. 2. 3. 4. Input SG.E (eb = single chroma = ec + 50 kHz) to pin 26. 2 Take the pin 33 output amplitude when "test mode" I C data is 1DH D6 = 1, D7 = 1 to be VRY. 2 Take the pin 33 output amplitude when "test mode" I C data is 1DH D6 = 0, D7 = 1 to be VBY. R/BN is defined as follows.
R-YN demodulation angle 1. 2. 3. 4. Input SG.E (eb = single chroma = ec + 5 kHz) to pin 26. 2 Take the pin 33 output amplitude when "test mode" I C data is 1DH D6 = 1, D7 = 1 to be VRY. 2 Take the pin 33 output amplitude when "test mode" I C data is 1DH D6 = 0, D7 = 1 to be VBY. R/YN is defined as follows.
* The vector is determined taking the demodulator gain into account.
Rev.1.0, Sep.23.2003, page 30 of 53
M61280M8-XXXFP TC1 TINT control characteristic 1 TC2 TINT control characteristic 2 1. Input SG.C (see figure below) to pin 26. Measure the absolute angle with reference to the pin 33 output voltage, referring to the figure below.
2. Take the TINT data center part (08H data 3CH) to be reference angle "TC", determine the TINT DATA maximum and minimum values. TC1 and TC2 are defined as follows.
TC1 = Tcmax - TC(deg) TC2 = TC - Tcmin(deg)
Ffsc fsc output frequency Vfsc fsc output amplitude 1. Input SG.C to pin 26. 2. Measure the pin 32 output frequency and amplitude. Ffscfree fsc output frequency in fsc free mode Vfscfree fsc output amplitude in fsc free mode 1. Input SG.C to pin 26. 2. Measure the pin 32 output frequency and amplitude with fsc free (07H D6) DATA 1. RGB Interface Block VBLK output blanking voltage 1. Input SG.A to pin 26. 2. Measure the voltage of the pin 50, 51, 52 pedestal and blanking parts.
Rev.1.0, Sep.23.2003, page 31 of 53
M61280M8-XXXFP GYmax contrast control characteristic 1 GYmin contrast control characteristic 2 1. Input SG.B (f = 100 kHz) to pin 26. 2. Measure the pin 50, 51, 52 output amplitude. GYEnor contrast control characteristic 3 GYEmin contrast control characteristic 4 1. Input SG.A to pin 26. 2. Measure the pin 50, 51, 52 output amplitude when applying 2.9 V and 0 V to pin 33. GYEclip contrast control characteristic 5 1. Input SG.F to pins 59, 60, 61, 65. 2. Minimize the contrast control data, and measure the output amplitude at and above the pedestal part of pins 50, 51, 52. The amplitude of the blanking part is not measured. Lum nor brightness control characteristic 1 Lum max brightness control characteristic 2 Lum min brightness control characteristic 3 1. Input SG.D (Vy = 0 V) to pin 26. 2. Measure the DC voltage other than the blanking part of the output of pins 50, 51, 52.
D(R)1 R drive control characteristic 1 1. Input SG.A to pin 26. 2. Measure the pin 50 output amplitude when the drive control data is at center and is maximum, take the results to beDRnor and DRmax respectively. 3. D (R) 1 is defined as follows.
D(B)1 B drive control characteristic 1 1. Input SG.A to pin 26. 2. Measure the pin 52 output amplitude when the drive control data is at center and is maximum, take the results to be DBnor and DBmax respectively. 3. D(B)1 is defined as follows.
Rev.1.0, Sep.23.2003, page 32 of 53
M61280M8-XXXFP D(R)2 R drive control characteristic 2 1. Input SG.A to pin 26. 2. Measure the pin 50 output amplitude when the drive control data is at center and is minimum, take the results to be DRnor and DRmin respectively. 3. D(R)2 is defined as follows.
D(B)2 R drive control characteristic 2 1. Input SG.A to pin 26. 2. Measure the pin 52 output amplitude when the drive control data is at center and is minimum, take the results to be DBnor and DBmin respectively. 3. D(B)2 is defined as follows.
EXD(R) digital OSD(R) input/output characteristic EXD(G) digital OSD(G) input/output characteristic EXD(B) digital OSD(B) input/output characteristic 1. Input SG.F (Vosd = 1.0 V) to pins 59, 60, 61, 65. 2. Measure the output amplitude at and above the pedestal part in pins 50, 51, 52. The amplitude of the blanking part is not measured.
EXD(R-G) digital OSD (R-G) amplitude difference EXD(G-B) digital OSD (G-B) amplitude difference EXD(B-R) digital OSD (B-R) amplitude difference 1. EXD (R-G), EXD (G-B) and EXD (B-R) are defined as follows.
EXD(R-G) = EXD(R) - EXD(G) EXD(G-B) = EXD(G) - EXD(B) EXD(B-R) = EXD(B) - EXD(R)
C (R) 1 R cutoff characteristic 1 C (G) 1 G cutoff characteristic 1 C (B) 1 B cutoff characteristic 1 C (R) 2 R cutoff characteristic 2 C (G) 2 G cutoff characteristic 2 C (B) 2 B cutoff characteristic 2 1. Input SG.D (Vy = 0 V) to pin 26. 2. Measure the DC voltage of other than the blanking part in the outputs of pins 50, 51, 52.
Rev.1.0, Sep.23.2003, page 33 of 53
M61280M8-XXXFP Ccon1 color control characteristic 1 Ccon2 color control characteristic 2 Ccon3 color control characteristic 3 1. 2. 3. 4. Input SG.C to pin 26. Measure the output amplitudes of pins 50, 51, 52 when IIC DATA 09H = 40h, take this to be Ccon0. Measure the output amplitudes of pins 50, 51, 52 under each set of conditions. Ccon1, Ccon2, Ccon3 are defined as follows.
MTXRB matrix ratio R/B MTXGB matrix ratio G/B 1. Input SG.G (rainbow color bar) to pin 26. 2. Measure the output amplitude when pins 50, 51, 52 are respectively VR, VG, VB. 3. MTXRB, MTXGB are defined as follows.
DOSD1 digital OSD switching characteristic 1 DOSD2 digital OSD switching characteristic 2 1. Input SG.F (Vosd = 1.0 V) to pins 65, 59, 60, 61. 2. Measure the rise time and fall time of the output signals of pins 50, 51, 52 at and above pedestal level. The blanking part is not measured.
Rev.1.0, Sep.23.2003, page 34 of 53
M61280M8-XXXFP BB(R) blue back function (R) BB(G) blue back function (G) BB(B) blue back function (B) 1. Input SG.A to pin 26. 2. Measure the output amplitude (p-p) of pins 50, 51, 52 other than the blanking part.
WB white raster function 1. Input SG.A to pin 26. 2. Measure the output amplitude (p-p) of pins 50, 51, 52 other than the blanking part.
WBL-RB white balance difference-RB WBL-GB white balance difference-GB 1. Input SG.A (Y = 30%L with burst) to pin 26. 2. Measure the pin 50, 51, 52 output white level potential from GND. Measured values are taken to be M1R, M1G, M1B respectively. 3. Input SG.A (Y = 30%: without burst) to pin 26. 4. Measure the pin 50, 51, 52 output white level potential from GND. Measured values are taken to be M2R, M2G, M2B respectively. 5. Calculate the differences in measured values. 6. Calculate the differences between calculated values of Rch and Bch with the Bch measured value as reference, defined as follows.
Rev.1.0, Sep.23.2003, page 35 of 53
M61280M8-XXXFP Deflection Block fH1 horizontal free-running frequency 1 fH2 horizontal free-running frequency 2 fH3 horizontal free-running frequency 3 1. Measure the frequency of pin 46 with no input. Hfree forced horizontal free-running operation 1. Input SG.A to pin 26. 2. Set H-FREE CONTROL DATA to on, measure the frequency at pin 46. FPHU horizontal pull-in range (upper) FPHL horizontal pull-in range (lower) 1. Input SG.H to pin 26. 2. Change the frequency of SG.H, measure the frequency range for which the pin 46 output signal and pin 26 input signal are pulled in, with respect to the video signal horizontal frequency. HPT1 horizontal pulse timing 1
HPT2 horizontal pulse timing 2 1. Measure the horizontal pulse timing using the method for HPT1. 2. Standard
HPT2 = (measured value) - HPT1
HPTW horizontal pulse width VH horizontal pulse amplitude
HSTOP horizontal pulse stop operation 1. Confirm that when H.START SW OFF (0FH:D7 = 0), the horizontal output goes low.
Rev.1.0, Sep.23.2003, page 36 of 53
M61280M8-XXXFP AFCG AFC gain operation 1. Measure the pin 43 output amplitude during AFC switching, taking the result when 12HD0 = 1, D1 = 1, D2 = 0 to be AFCtyp, and 12H D0 = 1, D1 = 1, D2 = 1 to be AFCmax. 2. AFCG is defined as follows.
fV vertical free-running frequency 1. Measure the pin 38 output frequency with no input. Vfree forced vertical free-running operation 1. Input SG.A to pin 26. 2. Set V-FREE CONTROL DATA to on, measure the pin 38 output amplitude. SCV service mode operation 1. Measure the pin 38 output DC voltage with the service switch on. FPVU vertical pull-in frequency (upper) FVPL vertical pull-in frequency (lower) 1. Change the SG.H vertical frequency, and measure the frequency when the pin 38 output waveform is pulled in. VRsi vertical ramp size VRsc1 vertical ramp size control range 1 VRsc2 vertical ramp size control range 2
VRpo1 vertical ramp position control range 1
Rpo1 vertical ramp position control range 2 1. Measure the vertical ramp timing using the same method as for VRpo1. 2. VRpo2 is defined as follows.
VRpo2 = (measured value) - VRpo1
Rev.1.0, Sep.23.2003, page 37 of 53
M61280M8-XXXFP VBLKW vertical BLK width
WVSS minimum width at minimum sync operation 1. Reduce the width of the SG.I signal, and measure the input signal width when the pin 38 output waveform pull-in is lost.
Rev.1.0, Sep.23.2003, page 38 of 53
M61280M8-XXXFP
Electrical Characteristics (MCU unit)
1. Electrical characteristics (unless otherwise noted, VDD = 5 V 5%, Vss = 0 V, f(XIN) = 8.95 MHz, Ta = -10 to 65C)
Limits Symbol ICC Item Power supply current During system operation Measurement Conditions Vcc=5.25V, f(XIN)=8.95MHz OSD OFF Data slicer off OSD ON Data slicer on Vcc=5.25V, f(XIN)=0, f(XCIN)=32kHz, OSD OFF, Data slicer off, Low power dissipation mode (CM5="0", CM6="1") During wait Vcc=5.25V, f(XIN)=8MHz Vcc=5.25V, f(XIN)=0, f(XCIN)=32kHz, Low power dissipation mode (CM5="0", CM6="1") When stopped VOH VOL "H" output voltage P11~P14, P20~P27, P40, P41 "L" output voltage P00~P07, P20~P23, P40, P41 P24~P27 P11~P14 VT+ - VT- Hysteresis (*1) RESET, INT1, INT2, INT3, TIM3,SIN, SCLK, SCL1, SCL2, SDA1, SDA2 "H" input leakage current P00~P07, P11~P14, P20~P27, P40~P45, RESET "L" input leakage current P00~P07, P11~P14, P20~P27, P40~P45, RESET I C-BUS bus switch connection resistance (between SCL1 and SCL2, SDA1 and SDA2)
2
Min. -- -- --
Typ. 15 30 60
Max. 30 45 200
Unit mA mA A
Measurement Circuit 1
-- -- -- 2.4 -- -- IOL=3mA IOL=6mA -- --
2 60 1 -- -- -- -- 0.5
4 200 10 -- 0.4 3.0 0.4 0.6 1.3
mA A
Vcc=5.25V, f(XIN)=0, f(XCIN)=0 Vcc=4.75V, IOH=-0.5mA Vcc=4.75V, IOL=0.5mA Vcc=4.75V, IOL=10.0mA Vcc=4.75V Vcc=5.0V
V V
2
V
3
IIZH
Vcc=5.25V, VI=5.25V
--
--
5
A
4
IIZL
Vcc=5.25V, VI=0V
--
--
5
A
4
RBS
Vcc=4.75V
--
--
130
5
Note:
1. when using P06, P07, P16, P23, P24, P25 as interrupt inputs or external clock inputs for timers, when using 2 P20 to P22 as serial I / O, and when using P11 to P14 as multi-master I C-BUS interface pins, there is hystersis.
Rev.1.0, Sep.23.2003, page 39 of 53
M61280M8-XXXFP 2. Test Circuit
A/D Converter Characteristics
(unless otherwise noted, VDD = 5 V 5%, Vss = 0 V, f(XIN) = 8.95 MHz, Ta = -10 to 65C)
Symbol - - - VOT VEST Item Resolution Nonlinear Diffierential Nonlinear error Zero-transition error Full-scale transition error IOL (SUM) = -0 mA Measurement Conditions Limits Min Typ Max 7 1.5 0.9 2 -2 Unit bits LSB LSB LSB LSB
Rev.1.0, Sep.23.2003, page 40 of 53
M61280M8-XXXFP
Pin Description
Pin no. 1 Name CNVSS Pin periphery Notes 0V
2 3
X IN XOUT
--
4 7
TEST1 TEST0
--
5 6 8
Vss (MCU) Vdd (MCU) FILT
-- --
Power source for MCU 0V Power source for MCU 5.0 V 5% --
9
HLF
--
Rev.1.0, Sep.23.2003, page 41 of 53
M61280M8-XXXFP
Pin no. 10
Name VHOLD
Pin periphery
Notes --
11
CVIN
--
12
RESET
--
13
MCU RESET OUT
H: 5.0 V L: 0.0 V
14
Y SW OUT
1.7 V
15
Video/Chroma GND
--
0.0 V
Rev.1.0, Sep.23.2003, page 42 of 53
M61280M8-XXXFP
Pin no. 16
Name X-TAL 3.58
Pin periphery
Notes 3.3 V
17
CHROMA APC FILTER
3.2 V
18
MCU 5.7VREG OUT
5.7 V Maximum outflow current = 2.5 mA
19 20 24 26
NC CVBS IN 3/2/1
-- 1.7 V
--
Rev.1.0, Sep.23.2003, page 43 of 53
M61280M8-XXXFP
Pin no. 21 25 27
Name AUDIO IN 3/2/1
Pin periphery
Notes 2.3 V
22 23
Video/Chroma Vcc MCU TEST
--
5.0 V 0V
28
5.7 VREG OUT
5.7 V Maxim outflow current = 5 mA
29
C IN
2.1 V
Rev.1.0, Sep.23.2003, page 44 of 53
M61280M8-XXXFP
Pin no. 30
Name Y IN
Pin periphery
Notes 1.7 V
31 32
VREG Vcc fsc OUT
--
8.7 V 3.0 V
33
INTELLIGENT MONITOR
Maxim outflow current = 100 A
34
AUDIO ATT OUT
3.5 V
35
AUDIO ATT FILTER
2.75 V to 3.25 V
36
TEST2
--
GND
Rev.1.0, Sep.23.2003, page 45 of 53
M61280M8-XXXFP
Pin no. 37
Name V RAMP FEED BACK
Pin periphery
Notes --
38
RAMP OUT
4.6 V Maxim outflow current = 1 mA
39
V RAMP CAP
--
40
8.7 VREG OUT
8.7 V Maximum outflow current = 1 mA
41 42
NC H VCO FEEDBACK
-- 3.0 V
--
Rev.1.0, Sep.23.2003, page 46 of 53
M61280M8-XXXFP
Pin no. 43
Name AFC FILTER
Pin periphery
Notes 3.5 V
44 45
DEF GND FBP IN
-- VTH: 1.0 V
--
46
H OUT
VOL: 0.0 V VOH: 5.4 V Maximum outflow current = 4 mA
47 48 49 50 51 52
DEF Vcc NC Hi Vcc R OUT G OUT B OUT
-- -- --
8V -- 8V --
Rev.1.0, Sep.23.2003, page 47 of 53
M61280M8-XXXFP
Pin no. 53
Name ACL/ABCL
Pin periphery
Notes --
54 59 60 61 65
TEST2 P42 P43 P44 P45
Use with only pin 54 open --
55 56 57 58
P14/SDA2 P13/SDA1 P12/SCL1 P11/SCL2
--
62 63 64 70
P00/PWM0 P01/PWM1 P02/PWM2 P07/INT1
--
66 67 68 69
P03/PWM3/AD1 P04/PWM4/AD2 P05/AD3 P06/INT2/AD4
--
Rev.1.0, Sep.23.2003, page 48 of 53
M61280M8-XXXFP
Pin no. 71 72 76 77 78
Name P40 P41 P23/TIM3 P24/TIM2 P25/INT3
Pin periphery
Notes --
73 74 75
P20/SLK/AD5 P21/SOUT/AD6 P22/SIN/AD7
--
79 80
P26/XCIN P27/XCOUT
--
Note: Voltage, current and other values appearing in the Notes column are reference values, and are not guaranteed rated values.
Rev.1.0, Sep.23.2003, page 49 of 53
M61280M8-XXXFP
Memory Layout Diagram
Rev.1.0, Sep.23.2003, page 50 of 53
M61280M8-XXXFP
Application Circuit
Notes:
Note:
Pin 54 should be kept open. If a crystal oscillator other than that recommended is used, the capacitance connected to X2 (3.58 MHz Xtal) must be studied. Connections to pins 55 to 80 may differ depending on conditions of use.
1. 2.
Rev.1.0, Sep.23.2003, page 51 of 53
M61280M8-XXXFP
Important Information
* Each application should be thoroughly studied and evaluated before making a decision. * 47 F and higher electrolytic capacitors and 0.01 F and higher ceramic capacitors should be connected in parallel between each of the power supply pins (6, 22, 31, 47, 49) and ground. In addition, it is recommended that the connections be made as close to the IC power supply pins as possible. 2 2 * When purchasing I C bus components, a license to use these components within a I C bus system is provided under 2 the I C patent rights of Philips Corp. 2 * However, the bus system must conform to the I C specifications stipulated by Philips.
Rev.1.0, Sep.23.2003, page 52 of 53
80P6U-A
JEDEC Code -- MD
e
MMP
Weight(g) Lead Material Cu Alloy
Plastic 80pin 1420mm body LQFP
M61280M8-XXXFP
EIAJ Package Code LQFP80-P-1420-0.8 HD
b2 ME
Package Dimensions
D
80 65
Under Planning
l2
64
24 25 40
41
E HE
A2
A3
b
x
M
Lp
Detail F
c
y
A1
Rev.1.0, Sep.23.2003, page 53 of 53
1
Recommended Mount Pad Symbol
A L1 F
e
A A1 A2 b c D E e HD HE L L1 Lp
A3
L
x y b2 I2 MD ME
Dimension in Millimeters Min Nom Max 1.6 -- -- 0.2 0.125 0.05 1.4 -- -- 0.32 0.37 0.47 0.125 0.175 0.105 13.9 14.1 14.0 19.9 20.1 20.0 0.8 -- -- 16.0 15.8 16.2 21.8 22.2 22.0 0.65 0.35 0.5 1.0 -- -- 0.6 0.75 0.45 -- 0.25 -- -- -- 0.2 -- -- 0.1 -- 0 8 -- -- 0.225 -- -- 10 -- 14.4 -- -- -- 20.4
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
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